The present invention relates generally to electronic devices. More particularly, the invention provides an improved package, packaging system and method for packaging of electronic devices. Merely by way of example, the present invention can be used for producing “small footprint sized packages” for integrated circuit devices and discrete devices often used for a variety of digital, analog, small signal discrete, and power applications, such as electronically controlled switches for power on/off control of system and sub-system components, and switching components in DC/DC conversion, especially in mobile and battery powered applications such as cell phones, portable and notebook computers, personal digital assistants (PDAs), digital cameras, and other computing applications, as well as in non-mobile applications such as set-top boxes, flat panel monitors; motherboards, desktop, server and main frame computers; in automotive electronics, and in cellular base station and in fiber and datacom networks.
A class of packages for microelectronic devices are “small footprint sized”, low pin count packages. Microelectronic circuits enclosed by these packages are in low- and medium integration level devices employing a low pin count. Such packages are often very small as compared to more conventional integrated circuit device packages (e.g., BGAs, PLCC, QFP, PGA) for conventional large DSPs (digital signal processors), ASICs (application specific integrated circuits), memory devices (e.g., Flash, DRAM, ROM) for computers, microprocessors (e.g., Intel™ Pentium), and the like, which often use very high pin counts and extremely large die sizes. Unlike such conventional integrated circuit device packages, small footprint sized, low pin count packages attempt to minimize footprint size as well as provide the minimum required pin count for a given type of product. With ever-increasing demands for enhanced performance, new applications for electronics often require such smaller sized packages and increased package efficiency as measured in performance per unit area of PC board. Such increased efficiency may take the form of smaller package footprints for a given performance level, or increased performance for an existing footprint. This increased need for space efficiency exists for discrete, power and small signal MOSFET and power control circuits, power management ICs, power ICs and analog ICs including electronic devices used in portable computer products and notebooks, portable telecommunication products, and portable entertainment products such as handheld games, MP-3 players, digital cameras (DSCs, camcorders), in lithium ion battery-pack protection electronics, and the like.
Although there has been much development with package designs for conventional devices, to date there has been little focus on improving the design of packages for the smaller, low pin count and low integration devices, especially for power applications. Many conventional small footprint packages still lack efficiency and performance. For example, conventional packages have not been configured to provide enhanced performance per unit area of PC board occupied. In many conventional packages, only 10 percent or less of the total available package footprint area on the PC board is occupied by an active semiconductor device. This poor area efficiency limits the functionality or performance of the semiconductor component in its application, especially when the available board space is determined by the maximum allowable size and three-dimensional form-factor of the end product, such as a cell phone. In this context, poor performance may constitute a lack of desirable features in the semiconductor (features not possible because of a limited amount of available silicon real estate), or as a higher resistance device, transistor, power MOSFET or other switching element leading to increased power losses, self heating, and further increases in resistance as a result of self heating. These increased power losses can be viewed as both a potential thermal problem, and as a loss in efficiency and battery life.
Furthermore, such small, low-pin count packages typically lack sufficient ability to remove heat from the semiconductor die and to conduct that heat out of the package into the PC board and into the ambient. The high thermal resistance characteristic of a package's inability to remove heat limits the utility of these conventional type small packages in applications (and in products) where the semiconductor die is forced to dissipate substantial power, even if but for a few seconds. In high power dissipation conditions, unless the power dissipation is limited, the semiconductor die may malfunction, or be damaged, and may also damage its own package and even other components in its vicinity on the PC board.
As a further limitation of such conventional packages, methods used to increase the number of potential pins on any given package, may in fact reduce the maximum die size that can fit into the package, and in so doing lead to even higher power losses and lower efficiencies.
It can also be shown, that adjusting the lead frame design in a conventional package to maximize the die size, may in fact lead to an inadequate number of pins to connect the IC or die, and may also result in the position of such pins and bond pads such that it becomes difficult or impossible to facilitate proper or optimal wire bonding.
Likewise, it can be shown that adjusting the number of pins for optimum bonding may result in a smaller die and poorer silicon performance, for example increasing the resistance in a power transistor, and in other cases, may result in a higher thermal resistance in a package with no convenient means to conduct heat out of the silicon and into the printed circuit board (PCB). This tradeoff may force an undesirable compromise between the number of pins and the thermal resistance and power handling capability of the package.
So in conventional type packages, there is an intrinsic tradeoff among factors such as the size of the die, the number of pins, the location of the pins relative to the die, the number of bond wires which may be bonded from any given pin and the bond length and the bonding angles which result, and the means to directly conduct heat through metal or through one or more leads into the PCB. Any or all of these factors make it difficult to achieve optimal performance for many IC and discrete devices, especially those involved in power applications or carrying high current.
As merely examples, we have provided some illustrations of conventional packages and their limitations below. For the purposes of the present invention, the term “lead frame” refers to electrically conducting portions of a package, apart from bond wires, that enable electrical communication with a die enclosed by a package. As a matter of terminology, the name “lead frame” includes both the pins and the die pad of the package because these elements are typically held together into a single inter-connected piece or frame until such time in the packaging process that the leads and the die pad are secured by the injection of plastic, after which the frame holding the leads and the die pad in place can be cut or disconnected. The term “die pad” refers to the portion of the lead frame in direct physical contact with the semiconductor die. Typically, the semiconductor die is attached to the die pad by a solder or adhesive material interposed between the die and the die pad.
Referring to FIGS. 1A–1F, illustrations of conventional six lead packages are shown. FIG. 1A is a simplified perspective view of conventional six-lead package 100 including package body 102 and exposed leads 104. FIG. 1B is a simplified plan view of conventional six-lead package 100 of FIG. 1A. FIG. 1C is a simplified plan view of conventional six-lead package 100 of FIG. 1A. FIG. 1C shows internal components such as lead frame 110 including die pad 106 and internal portion 104a of leads 104. FIG. 1D is a simplified plan view of the conventional six-lead package of FIG. 1A additionally showing die 108 and bond wires 110. Bond wires 110 permit electrical communication between die 108 and leads 104. Since the package has six independent leads 104, it is electrically a six pin package. Thermally it is a “zero” pin package since none of the pins connect directly to the die pad and so that there is no direct path for heat to flow from the die to the PC board.
As shown in the figures, the die pad occupies a very small region of the entire area of the package, including outer portions of the leads. The conventional package occupies less than 10% of the entire package footprint on the PC board, which is undesirable for today's high performance applications. The conventional package is also not configured in a manner to efficiently draw away thermal energy that may dissipate or build up in certain types of power integrated circuits and in discrete power devices. Accordingly, conventional six lead packages have many limitations.
FIG. 1E is a simplified plan view of a configuration of a conventional six lead package like that shown in FIG. 1D having a lead frame modified to (somewhat) reduce the thermal resistance of the package. Specifically, package 120 of FIG. 1E shows five leads 122 connected to die 124 by bond wires 126, and sixth lead 128 integral to die pad 130. Because of its greater area of contact with die pad 130, integral lead 128 permits a larger quantity of thermal energy to be drawn away from operating die 124 through die pad 130 and then to be dissipated into the external environment. The improvement in thermal resistance is somewhat mitigated by the limited cross-sectional area of a single package lead (through which heat must flow) and on the limited contact area and surface area of the lead where it contacts the PC board. The limited contact area between the board and a single lead means the heat enters the PC board in a small region, like a thermal “point source”. The heat spreading into the board from a point source is redistributed across the PC board's surface less efficiently than if a larger lead or, even better, multiple leads were to carry the heat from the die to the PC board. Accordingly a single lead, such as 128, connected directly to the die pad, while improving thermal resistance, results in less improvement than expected and depends heavily on the PC board layout. Although a larger pin (or multiple pins) carrying heat would be less sensitive to the influence of the board layout on the resulting thermal resistance, such design features are not available or anticipated by conventional packages. Another drawback with this configuration of a six-lead package is it still lacks an ability to efficiently use package space. Specifically, only 10% of the available footprint area is occupied by die 124. The remainder of the footprint area is allocated to other, nonperformance-related considerations, especially to satisfy all the mechanically related design rules
FIG. 1F shows a simplified cross-sectional view of the conventional six-lead package 100 of FIG. 1D, along line 1F–1F′. The cross-sectional view of FIG. 1F shows package body 102 enclosing die pad 106 and semiconductor die 108. Leads 104 projecting from package body 102 include portions 104a internal to package body 102, a distance requiring some minimum dimension to insure that the plastic molding of the package is sufficient to hold the lead 104 tightly in place. Lead portions 104b are external to package body 102, a dimension requiring some minimum distance needed to facilitate bending the lead without cracking or otherwise damaging the molded plastic package. Foot portions 104c of leads 104 are in contact with trace 112 of underlying PC board 114, to guarantee some minimum contact area between the foot and the PC board's conductive trace. The forming and bending of lead 104 including the bent portion of the lead and the minimum sized foot are determined by mechanically-related design rules chosen to produce repeatable results at rapid manufacturing through-put rates consistent with the use of industry standard machines commonly used in semiconductor packaging.
FIG. 2A shows a simplified cross-sectional view, including dimensions, of the conventional six-lead package of FIG. 1D, also along 1F–1F′. Dimensions indicated in FIG. 2A include die width (Wchip) of die 108, package body width (Wbody) of plastic body 102, package body thickness (Zpkg) of plastic body 102, vertical package profile (Zprofile) of package 100, and lead foot width (Wfoot) of lead 104, and clearance (gap) Z1 between the bottom of package body 102 and metal trace 112 located on PC board 114.
FIG. 2B shows a simplified plan view, including dimensions, of conventional six-lead package 100 of FIG. 1D. Dimensions indicated in FIG. 2B include the aforementioned package body width (Wpkg), die width (Wchip), length (X3) of internal lead portion 104a, and width (Wfoot) of lead foot 104c, along with additional design dimensions including distance (X2) between internal lead portion 104a and die pad 106 (a gap needed to prevent shorting between the pin and the die pad), setback or inset (X1) of die 108 from edge of die pad 106 (a minimum dimension needed to make sure the die doesn't substantially hang over or extend beyond the die pad), and width (X4) of external lead portion 104b (needed to facilitate bending and forming of the lead after plastic molding occurs).. The package shown in FIG. 2B further elaborates the rules governing the construction of package 100 (shown previously in FIG. 1D), and therefore suffers from the same inefficient use of space as described above in conjunction with FIG. 1D.
FIG. 2C shows a simplified plan view, including dimensions, of conventional six lead package 100 of FIG. 1D as occupying footprint 110 on PC board 112. In this figure, each lead 104 of the package lead includes foot 104c sitting atop and contained within a portion of a PC board conductive trace 114 (shown here as a rectangle to represent the minimum possible dimension of the conductive trace). In practice these traces continue in various different directions, connecting to other elements on the PC board. The minimum spacing around the lead foot 104c however can be simply estimated as a border or “enclosure” rule of dimension X5. The intention of this exercise is to relate the physical dimensions of the PC board occupied by the package (in Cartesian nomenclature as (Wpcb, Vpcb)) to the actual semiconductor die dimensions (Wchip, Vchip). Dimensions labeled in FIG. 2C are summarized in TABLE 1 below
TABLE 1DIMENSIONS LABELED IN FIG. 2CLABELDESCRIPTIONWpcbwidth of package footprint 110Vpcblength of package footprint 110Wchipwidth of die 108Vchiplength of die 108Wbodywidth of package body 102Vbodylength of package body 102X5setback of lead foot 104c from edge of trace 112X2distance between edge of die pad 106 and internal portion 104aof lead 104Wleaddistance between ends of opposite lead feet 104cX4width of external portion 104b of lead 104X3width of internal portion 104a of lead 104Wfootlength of lead foot 104cX8setback of die pad 106 within package body 102From the above definitions it can be seen the following geometric rules define the package's body dimensions as a function of the chip dimension as approximatelyWbody=2*X3+2*X2+2*X1+WchipVbody=2*X8+2*X1+VchipAnd determines the package footprint on the PC board as approximately given byWpcb=2*X5+2*Wfoot+2*X4+WbodyVpcb=VbodyThe package shown in FIG. 2C exhibits the same inefficient use of space as described above in conjunction with FIG. 1D, except that now the wasted space outside the package becomes more evident.
FIG. 3A is a simplified plan view of an alternative configuration of a conventional six-lead package, showing internal components of package body 301. Package 300 includes three leads 302, 304, and 306 integral with die pad 308. Leads 310, 312, and 314 are each connected to die 316 by bond wires 318. The one-sided orientation and surface area provided by integral leads 302, 304, and 306 enables heat flow from operating die 316 and out of package body 301, to be dissipated in the external environment, thereby improving the thermal resistance of the package. The pins connected directly to the die pad are herein referred to as “thermal pins” because they carry heat away from the die and into the PC board. Note that even through leads 302, 304, and 306 comprise three thermal pins, they represent only a single electrical pin since they are all shorted to a single potential, namely the die pad potential.
So increasing the number of pins connected directly to the die pad improves the package's electrical thermal resistance but at the penalty of decreasing the number of leads available for distinct electrical connections. Furthermore, even with this modified lead frame conventional package configuration shown in FIG. 3A still suffers from inefficient utilization of footprint area, as die 316 occupies only approximately 10 to 15% of the total available footprint area.
Another limitation of this conventional package, is its number of electrically independent pins, which as shown comprises 4 distinct electrical connections, the three separate pins 310, 312, and 314, and the die pad connected pins 302, 304, 396 constituting a fourth connection. So this modified package is a 4 electrical pin, 3 thermal pin package. While a 4 electrical pin package is often applicable for the packaging of discrete transistors, many ICs need more pins to include various control functions
FIG. 3B is a simplified plan view, including dimensions, of the package shown in FIG. 3A. Dimensions labeled in FIG. 3B are summarized below in TABLE 2.
TABLE 2DIMENSIONS LABELED IN FIG. 3BLABELDESCRIPTIONWleadwidth between lead feet ends on opposite side of package 300Vleadlength between lead feet on opposite ends of the same side ofpackage 300Wchipwidth of die 316Vchiplength of die 316Wbodywidth of package body 301Vbodylength of package body 301X7width of internal portion of integral leads 302, 304, 306X2distance between edge of die pad 308 and internal portion ofnon-integral leads 310, 312, 314Wleaddistance between ends of opposite lead feet 104cX4width of external portion of non-integral leads 310, 312, 314X3width of internal portion of non-integral leads 310, 312, 314Wfootlength of lead footThe package shown in FIG. 3B exhibits the same inefficient use of space as described above in conjunction with FIG. 3A.
FIG. 3C is a simplified plan view of another alternative configuration of a conventional six lead package. Like the package embodiment shown in FIG. 3A, package 350 includes three leads 352, 354, and 356 positioned on the same package side that are integral with die pad 358. Two of the remaining leads 360 and 362 are integral with one another and connected to die 364 through bond wires 366. Sixth lead 368 is connected to die 364 by bond wire 369. As described above in conjunction with the embodiment shown in FIG. 3A, the three integral leads 352, 354, and 356 offer the advantage of unidirectional flow and enhanced dissipation of heat generated by die 364. Formation of leads 360 and 362 out of a single piece of metal creates space for an additional third bond wire to connect leads 360 and 362 to die 364. The resulting package has 3 electrical pins and 3 thermal pins.
The additional bond wire results in a lower resistance electrical contact with die 364. However, the package shown in FIG. 3C exhibits the same inefficient use of space as described above in conjunction with FIG. 3B, in that die 364 occupies only 10 to 15% of the total available footprint area.
FIG. 3D is a simplified plan view of yet another configuration of a conventional six lead package, showing internal components of package body 371. Package 370 includes four leads 372, 374, 376, and 378 that are integral with die pad 380. One of the remaining leads 382 is connected to die 385 through bond wire 384. The other remaining lead 384 features a lengthy internal portion 384a that is connected to die 385 through multiple bond wires 387. As described above in conjunction with the package embodiment shown in FIG. 3A, leads 372, 374, 376, and 378 integral with die pad 380 offer the advantage of enhanced heat dissipation from die 385. Elongated lead 384 offers the advantage of multiple bond wire connections and reduced resistance. However, the package shown in FIG. 3D exhibits the same inefficient use of space as described above, in that die 385 occupies only 10% to 15% of the total available footprint area. The resulting package has 4 thermal pins but only 3 electrical pins.
FIG. 3E is a simplified plan view of still another configuration of a conventional six lead package, showing internal components of package body 391. Package 390 includes four leads 392, 393, 394, and 395 integral with die pad 396. The remaining two leads 397a and 397b comprise opposite ends of a single metal piece that is connected to die 399 through multiple bond wires 398. Unlike the similar, previously illustrated embodiments package 390 of FIG. 3E includes only two contacts to die 399, which can perform the function of a simple device such as a diode. Package 390 is therefore a six-leaded package with 4 thermal pins but only two electrical pins. Furthermore, package 390 shown in FIG. 3E exhibits the same inefficient use of space as described above, in that die 399 occupies only 10% to 15% of the total available footprint area.
While the conventional packages described so far utilize six leads, other types of conventional packages may utilize a different number of leads. For example, FIG. 4A is a simplified perspective view of a larger footprint conventional eight lead package. Package 400 includes package body 402 and exposed leads 404. Like the previously described six lead package, the leads of this package type must be bent to connect to the PC board with the foot of each lead being substantially co-planar.
FIG. 4B is a simplified plan view of the eight lead package of FIG. 4A, showing internal components within package body 402. Specifically, package 400 includes first die 406 positioned on first die pad 408, and second die 410 positioned on second die pad 412. First die 406 is connected to leads 404a–d through bond wires 411, and second die 410 is connected to leads 404e–h through bond wires 415. Package 400 is therefore a dual die eight lead package offering a total of 8 electrical pins but no (zero) thermal pins. Like the conventional six-lead packages described above, conventional eight-lead package 400 also suffers from inefficient use of available footprint area, in that even less than 10% of the total package footprint is occupied by dies 406 and 408.
FIG. 4C is a simplified plan view of another configuration of a conventional eight-lead dual package, showing internal components within package body 421. Package 420 includes first die 422 positioned on first die pad 423, and second die 426 positioned on second die pad 428. First die 422 is connected to leads 404a–c through bond wires 425, and lead 404d is integral with first die pad 423. Second die 426 is connected to leads 404e–g through bond wires 429, and lead 404h is integral with second die pad 428. Package 420 is therefore a dual die eight lead package offering a total of 8 electrical pins with only two thermal pins (one per each die). While integral leads 404d and 404h offer the advantage of some degree of enhanced heat dissipation from dies 422 and 426, respectively, package 420 suffers from the same inefficient allocation of footprint area as the package of FIG. 4B.
FIG. 4D is a simplified plan view of another configuration of an eight-lead dual package, showing internal components within package body 431. Package 430 includes first die 433 positioned on first die pad 432, and second die 435 positioned on second die pad 436. First die 433 is connected to leads 434c–d through bond wires 437, and leads 404a–b are integral with first die pad 432. Second die 435 is connected to leads 404g–h through bond wires 439, and leads 434d–e are integral with second die pad 436. Integral leads 434a–b and 434e–f offer the advantage of enhanced heat dissipation (conduction into the PC board) from dies 433 and 435, respectively. Package 430 is therefore a dual-die eight-lead package offering a total of 6 electrical pins but with 4 thermal pins (two per die pad). However, while dies 433 and 435 are shown as being somewhat larger in area than the dies of FIG. 4C, package 430 exhibits the inefficient allocation of footprint area as the package of FIG. 4C.
FIG. 4E is a simplified plan view of a configuration of an eight-lead package enclosing a single die, showing internal components of package body 441. Package 440 includes elongated die 442 positioned on die pad 446 and in communication with each of leads 444a–h through bond wires 448. Like all of the conventional packages described above, package 440 suffers from the same inefficient allocation of footprint area. Specifically, die 442 occupies less than 10% of the total footprint area available to the package. Moreover, the aspect ratio (the ratio of length to width) of the maximum possible die size to fit in this package may be too extreme (over a 3-to-1 ratio of dimensions). High aspect ratio die can exhibit poor die attach and increased incidence of die cracking and stress related failures. Package 440 is a single-die eight-lead package offering a total of 8 electrical pins but no (zero) thermal pins. So the number of thermal pins is compromised in order to increase the number of electrical pins.
FIG. 4F is a simplified plan view of still another configuration of an eight-lead package enclosing a single die, showing internal components of package body 451. Package 450 includes elongated die 452 positioned on die pad 456 that is integral with leads 454a–d. Three of the remaining leads 454e–g are formed from a single piece of metal that is connected with die 452 through multiple bond wires 457. Remaining lead 454h is connected with die 452 through bond wire 459. As described above, the four integral leads 404a–d offer the advantage of enhanced heat dissipation (heat conduction into the PC board). Formation of leads 404e–f out of a single piece of metal offers the advantage of multiple bond wire connections offering reduced electrical resistance. Package 450 is therefore a single-die eight lead package offering a total of 3 electrical pins with 4 thermal pins. Despite these advantages however, package 450 offers the same relatively poor utilization of footprint area as the conventional package shown in FIG. 4E, as well as exhibiting a high aspect ratio of die length to die width.
While the above embodiments of a conventional package are functional, each suffers from the disadvantage of inefficient utilization of space afforded by the package footprint. Specifically, TABLE 3 shows die area versus footprint area for single-die conventional packages of five standard types:
TABLE 3Lead-PackagePackageDie/LeadBodyFootprintBodyDieDieDieFootprintPackageWidthLengthAreaWidthWidthLengthAreaAreaType(mm)(mm)(mm2)(mm)(mm)(mm)(mm2)(%)SO-864.8328.983.812.493.969.860434MSOP-84.93.014.73.01.692.133.624TSOP-62.853.058.69251.650.651.781.15713SOT-232.537.51.350.351.730.60558SC-702.124.21.250.251.40.358
TABLE 3 shows that even in the largest package, the enclosed die occupies less than 35% of the total footprint area. In the two smaller packages, the die occupies a mere 8% of the total available area of the package footprint. In order to maximize the space efficiency of the package, it is therefore desirable to redesign the package to allocate as much space as possible to the die. Likewise, it is desirable to redesign the package to offer the lowest possible thermal resistance and the maximum number of die-pad connected thermal pins without sacrificing the number of available distinct electrical pins. It is also desirable to redesign the package to minimize the aspect ratio for any given die area, and to maximize the number of available bond wires. Finally it is desirable to redesign the package for the most flexible and optimum bonding of the wire bonds, and to be able to maximize the number of bond wires for a given pin if the pin is carrying high current. Accordingly, there is a need for improved packaging systems and methods.